A raised source/drain of a semiconductor device such as a transistor generally refers to a source/drain with a raised source/drain layer (which forms at least a portion of a source or a drain thereof) above a surface of a substrate that provides a foundation for the transistor. Often-times, the raised source/drain is employed in transistors such that a metal contact is vertically offset from a surface of the substrate and a junction of the source/drain (also referred to as a “source/drain junction”) by the addition of epitaxially grown semiconductor material. As a result of the vertical offset, source/drain junction leakage (a component of an overall leakage of the transistor) and parasitic source/drain series resistance (which degrades a current drive of the transistor) are reduced.
Constructing the raised source/drain, however, may give rise to certain challenges associated with a design of the transistor or, for that matter, any semiconductor device employing the same. For instance, the raised source/drain layer of the source/drain is typically formed by selective epitaxial growth such that film nucleation and growth occurs only on exposed areas of a crystalline substrate while preventing nucleation and growth on exposed adjacent dielectric layers. Selective epitaxial growth conditions by definition maintain high interfacial energy between the epitaxially grown material and the dielectric surface. Therefore, facets frequently form on edges of the raised source/drain layer to minimize an interfacial area with an adjacent dielectric material such as an oxide or nitride spacer about a gate of the transistor.
On a conventional transistor fabricated on a (001) substrate wherein the gate is oriented along the <110> direction, the facets are most commonly oriented along the {111} and {311} planes. Typically, a shape of the raised source/drain facet is constrained by a growth rate of a facet plane thereof. For example, inasmuch as a {111} plane has a relatively slower growth rate than other planes, the facet associated therewith tends to expand horizontally. As a result, the facets may cause a gap between the spacer and the raised source/drain layer formed about the gate.
If the gap between the raised source/drain layer and spacer is not attended to, subsequent formation of a silicide may create a spike penetrating through a source/drain junction that may ultimately short circuit the source/drain to the substrate. Additionally, inasmuch as the source/drain is typically formed by an ion implantation process after the spacers are formed, a depth of the source/drain junctions is influenced by the facets. For a better understanding of transistors employing raised source/drains, see, for instance, U.S. Pat. No. 4,998,150, entitled “Raised Source/Drain Transistor,” issued Mar. 5, 1991, to Rodder, et al., and U.S. Pat. No. 6,137,149, entitled “Semiconductor Device having Raised Source-Drains and Method of Fabricating the same,” issued Oct. 24, 2000, to Kodama, both of which are incorporated herein by reference.
The growth of the facets during the selective epitaxial growth process has been the subject of many references including a reference by Akihiko Ishitani, et al. (Ishitani) entitled “Silicon Selective Epitaxial Growth and Electrical Properties of EPI/Sidewall Interfaces,” Japanese Journal of Applied Physics, Vol. 28, No. 5, May 1989, pp. 841–848, which is incorporated herein by reference. Ishitani proposes a silicon selective epitaxial growth process employing <100> oriented isolation structures (such as the spacers about the gate and the shallow trench isolation regions in the substrate) to suppress facets and stacking faults. Through the course of study, Ishitani observed facet-free selective epilayers proximate <100> oriented isolation structures. In accordance therewith, a reduction in a P-N junction leakage is experienced with devices employing the <100> oriented isolation structures. The reduction in the junction leakage is related to the facet free epilayers.
Therefore, it appears that reducing the number of facets associated with the selective epitaxial growth of the raised source/drain of a transistor has significant benefits to an operation thereof. More specifically, suppressing facet formation during the selective epitaxial growth of a raised source/drain is beneficial to reducing a junction leakage at the source/drain junction. As mentioned above, otherwise, unwanted salicide and dopant penetration may occur at the corners of the facets leading to potential short circuits. Stacking fault formation at the selective epilayer/dielectric interfaces is also possible depending on an orientation of the structures that form the transistor.
Accordingly, what is needed in the art is a semiconductor device such as a transistor and related process of forming the transistor that reduces the effects of facets on the edges of a raised source/drain that overcomes the deficiencies in the prior art.